This invention relates to integrated circuit random access memory devices, and more particularly, to techniques for configuring the depth and width of a region of random access memory.
Integrated circuit random-access memory (RAM) devices are widely used in electronic systems. Such memory devices are typically characterized by a depth and a width. The width of a device is the number of parallel data output lines available for reading out data stored in the device. The depth of a device is the maximum number of data bits that may be accessed via each of the data output lines. For example, devices with a total storage capacity of two kilobits of data are available in 2Kxc3x971 and 1Kxc3x972 configurations. A 1Kxc3x972 device has a width of two and a depth of 1 kilobit (1024 bits). A 2Kxc3x971 device has a width of one and a depth of two kilobits.
Because random-access memory devices are available in various depth and width configurations, a designer of an electronic system is generally able to select a memory device with a depth and width suitable for use in the system. However, in some applications it would be desireable desirable to be able to reconfigure the depth and width of a selected memory device without having to use an entirely new part.
In addition, programmable logic devices sometimes contain regions of RAM, as described in commonly assigned co-pending Cliff et al. U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, which is hereby incorporated by reference herein. Programmable logic devices can be programmed by a user to perform a variety of logic functions. To enhance the flexibility of a programmable logic device containing a region of RAM, it would be useful if were possible to program the region of RAM to various depth and width configurations.
Gate arrays sometimes contain blocks of RAM. If only part of the block of RAM is connected to the logic circuitry of the gate array during fabrication, the depth and width of the RAM that is used can be varied. For example, if a gate array contains a 2Kxc3x972 RAM array block, it is possible to fabricate the connections between the gate array logic circuitry and the RAM so that only a 2Kxc3x971 region of RAM is used. Alternatively, the gate array can be fabricated so that only a 1Kxc3x972 region is used. However, selectively connecting only portions of the block of RAM to the logic circuitry of the gate array is inefficient, because the portion of RAM that is not connected to the logic circuitry cannot be used. Further, because gate arrays are generally configured using custom masks, they are not field programmable and cannot be reconfigured after fabrication.
Some gate arrays, known as field programmable gate arrays, are reprogrammable. Field programmable gate arrays typically contain numerous configurable logic blocks, each of which may contain a small amount of RAM. Although it might be possible to connect a number of the configurable logic blocks together to provide a large region of RAM, such an arrangement is unlikely to be satisfactory. The process of passing signals to and from a configurable logic block is relatively slow. Further, field programmable gate arrays do not contain row and column decoders for addressing RAM arrays. Although some decoding functions might be provided by the configurable logic blocks, using configurable logic blocks to build decoders would be cumbersome. Using the configurable logic blocks for decoding would also be slower than using dedicated row and column decoder circuitry.
It is therefore an object of the present invention to provide a programmable random-access memory circuit.
It is a further object of the present invention to provide a variable depth and width random-access memory circuit.
These and other objects of the invention are accomplished in accordance with the principles of the present invention by providing a programmable variable depth and width random-access memory circuit. The memory circuit contains rows and columns of memory cells for storing data. Row and column address circuitry is used to address the cells. Output circuitry is used to route data from the array to one or more data output lines.
The row address circuitry contains a row decoder. A row address signal is provided to the row decoder that causes the row decoder to address an individual row of memory cells in the array.
The column address circuitry receives a column address signal and a depth and width selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells in the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a routing array having a pattern of fixed connections and by a group of programmable multiplexers.
The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.
If desired, the random-access memory circuit can be provided as part of a programmable logic device that uses programmable RAM or as part of any other suitable integrated circuit. The random-access memory circuit can also be provided as a discrete integrated circuit device.